Back to main EPROM page|
A13 circuit modification schematic It will open in a separate floating window. All the pictures in a gallery page on this site A13 Problem in detail: The original circuit has much too slow dU/dt on A13, ZIF pin 26. Going on (risetime) = 40 usec, going off (falltime) = > 60 usec. That's why the 1000H 2000H 3000H 4000H a.s.o. errors occurred. The A13 level change is only stabilized after a second succesive read, at the second address!!! The previous address information is lost........ There is also a too heavy DC load: max. U-A13 = 2.75V. Lowering R12 to give a voltage rise doesn't help much. Cause is a parasitic current path through the 7805 and the ballast R! A design flaw!! Adding series diodes as in this update to the 7805 and only changing the Q7 circuit to a PNP driver from +5V (with a BC640) gives indeed some minor improvements, a faster rise and higher A13 values, but still the discharge / fall times are wrong. See for yourself if you have an oscilloscope nearby and perform a read master test. Trigger on A13 (pin 26) on one channel, put A0 (pin 10) on the other as a reference. Connect to the ZIF unit with small pieces of isolated wire in it; keep it save. Do this twice: one time for positive and one time for negative going triggering. If you have a scope with memory available: even much better. Or look over here for a scope snapshot. So a complete rebuild around this pin 26 appeared necessary: Due to the fact that a high capacitive load will remain (the Vcc decouple C's), I've chosen a power MOSFET driver from MAXIM, a MAX 626 (= improved TSC 426), intended to drive a capacitive load with high currents without problems. MAX 626 has two inverting buffers, I used them in parallel, that's allowed. The MAX628 (= TSC428) has one inverting and one NON-inverting buffer, if used: ground the unused buffer input. (The MAX 627 (TSC 427) has two NON-inverting buffers: good for the 904BN version) To reduce +5V Vcc dropout spikes: charging is done via the 22 Ohm R and the BAV21 diode. Also: supply bypassing is extremely important: extra 4.7uF tantalum + 100nF ceramic. To avoid a parasitic ballast R on Vcc with a series diode and not without. Discharge via the 180 Ohm R and a speedup C of 180 nF. The 180 Ohm R is no problem in the event the 5 V remains on. The 180 nF parallel C gives capacitive compensation just like the C's in an oscilloscope probe. With the proper value it compensates the Vcc capacitors in the ZIF socket completely. Giving a nice rectangular square wave despite a heavy capacitive loading. To avoid undershoot pulses on the A13 line (if not 100% in balance) a schottky diode, BAT41, is added in the ZIF socket unit, in an open space for a ballast R. First I used a too high compensation C (1uF), giving a small undershoot pulse of 0.4V but a bit faster falltime. A value of 150 nF (rectangular) to 330 nF (a small undershoot dip) should be chosen. Tests were done with 150 nF, later 180 nF was chosen. The 7805 circuit on the A13 pin, used as Vcc in 2716 and 2732 mode, is separated from A13 mode with a simple diode. The small loss in voltage is compensated with an extra diode in the ground pin. A stabilising larger capacitor is also direct to the 7805. This circuit change is in use for many years on a 486DX-2 without any problem. No 1000H 2000H a.s.o. error has ever occurred after the change. The delays are now smaller than 1 usec!! new and old risetime (old a little shifted) and going off, new falltime Occasionally there are misprogrammings (probably after a bad erasure?, who has none??) , but a dummy blank check (without EPROM) before a real one sets all the internal settings OK. Besides the above improvements on A13 there are also some changes made in the Vpp output circuits. The fall time from Vpp to Vcc is a bit too slow (delays should be halved), /CE comes too quick. This Vpp to Vcc jump is repeated every program pulse : program, verify, program, verify, a.s.o., also checked with an oscilloscope. The slow fall time (with /CE nearby) could "kill" an EPROM on a 486 PC, maybe killing is not the right term: unwished programming a not wanted 00H. More ballast with a reduced R in place of the existing ones improves these Vpp delays to half of them: < 10 usec. The address fall times went down from 15 usec to about 5 usec by placing lower Vpp ballast R's. (3x 2K2 and 1x 2K7 were they were 4x 6K8) The series diodes in some output lines are replaced by schottky types, this gives 0.3 to 0.4 V more margin. Also two pull-up R's were added. Address voltage dropped from near 5 to 4 Volts, with the schottky diodes added. See schematic for details. With the standard diodes the voltage drop is a bit more... The TL 497 (U1) circuit has had many minor changes. See a separate page for those improvements. Due to the lower ballast R's there is more power drain from the Vpp supply. This was no problem after the TL497 circuit changes. Success with the rebuild of your programmer.... Walter Geeraert Vlissingen The Netherlands walterg@cumail.nl |
Copyright© 1990 - 2024 Walter Geeraert - All Rights Reserved
|
Back to main EPROM page |